Abstract
The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to the process of SPCE061A single chip core control and task scheduling; FPGA for external expansion, internal self-system bus, address decoding the full translation code approach. There DDS internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table; DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal. Sweep signal of 30MHz for the FPGA system clock frequency and external phase-locked loop (FPGA using FLEX10K10 no internal phase-locked loop) frequency, high frequency stability, amplitude stability of the sweep signal. Amplifier parameters measured by reference to the standard GB3442-82, low-frequency signal amplitude measurements taken by sampling high-speed AD and then proceed to the method of digital processing; high-frequency signal directly proportional to the magnitude of the integrated chip measured RMS conversion. A / D conversion using internal SPCE061A own 10 of the AD. SPCE061A main user interface (keyboard scanning, liquid crystal display, data printing and other services for the activation process), AD conversion, and measurement parameters (Vio Iio Kcmr Avd BWG Tr), the host computer and communications functions. PC main crew sent down measurement instructions, and under the exchange of measurement data-bit machines, as well as data storage, playback, and Statistics.
Key words：measurement of operational, amplifier parameters, DDS, FPGA, SPCE061A, digital
signal processing
