In the communications system,to guarantee the timing information's quality, prevent the influence of the long company 0 and links 1 pair to the transmition of the synchronization, we need to add harassing code to the data in the transmitting and carrying on the solution to harassing code to the receiving .
The present paper is introducing the principle of harassing code and the solution in the digital communication, using the CPLD chip to harass the design to carry on the scrambler reconciliation. The simulation graph and the oscilloscope are obtained through the MAX+plus II software the profile which obtains to the circuit wafer debugging carries on the comparison, confirms this design the accuracy. This design has the high using value to study the content suits of the current science and technology the development.
Key word: CPLD, MAX+plus II,VHDL, Harasses the code, The solution harasses