基于PCI接口测试系统设计

电气自动化论文编号:ZD375  论文字数:15900,页数:30，有任务书 
 
目录
摘  要 1
Abstract 1
前言 2
一  绪论 4
1.1 选题背景 4
1.2 图像处理技术的应用与发展 4
1.3 PCI总线 5
1.3.1 PCI总线的特点和主要性能 6
1.3.2 PCI总线信号定义 7
1.3.3 PCI总线命令 13
1.3.4 基本的PCI总线协议 14
1.3.5 PCI总线传输 15
1.4 PCI接口的技术难点 15
二  方案设计论证 16
2.1 功能分析 16
2.2 元件选择 17
2.3总体框图 18
三 设计内容 18
3.1 信号产生模块 18
3.1.1时钟产生电路 19
3.1.2白噪声信号发生器 19
3.1.3 分频器 19
3.1.4 移位寄存器 19
3.1.5 FIFO 19
3.2  PCI9030 20
3.3 MEMORY模块 25
3.4  PCI CONNECTOR 模块 26
第四章 小结与致谢 28
第五章  参考文献 29

摘  要：基于PCI接口测试系统设计的目的主要将噪声信号产生器产生的信号、存储、经PCI接口送入主机，PCI部件和插卡是独立于处理器的，这种独立性使PCI总线可以最优化I/O功能，使处理器/内存系统和各种高性能的外设可以并发执行PCI局部总线操作.PCI总线是一种即插即用的总线标准，支持全面的自动配置，最大允许64位并行数据传送,采用地址/数据总线复用方式，最高总线时钟可达66MHz，支持多总线结构和线性突发(Burst)传输，最高峰值传输速度可达128MB/s。

关键词：专用集成电路，PCI局部总线

Design of testing system for PCI Interface

Abstract：This design is main the signal of the machine creation, saving, was connected by PCI send into the host, The components and jack of PCI is independence with processor, so it can sustain some processors, even the processor in the future. PCI bus with the independence can optimize the function of I/O most, and make system of processor/memory and all kinds of high performance exterior equipments execute the operations of the PCI Local Bus. The total line in PCI is the total line standard of a kind of plug-and-play, supporting to install automatically completely, biggest allow 64 proceeds together the data delivers, adopting the total line in address/ data reply to use the way, the tallest total line clock can amount to 66 MHz, support many total lines construction is abrupt to deliver with the line, the high peak value delivers speed can amount to 128 MB/ s.
 
Key Word：ASIC, PCI Local Bus