Abstract
The system is designed for data multiplexed and de-multiplexed. It is based on TDM. The system includes the transmitter and the receiver. They are implemented mainly by FPGA. There are three inputs in the transmission system: data from A/D converter, DIP1 and DIP2. The three channels are out serially and time-divisional under the FPGA’s control. The FPGA in the transmitter is divided into four modules which are frequency divider, Barker generator, data multiplexer and voltage display. Voltage display is used for processing the data converted by ADC and sending it to the LED. The serial data are serial shifted into the FPGA in the receiver. Bit-synchronize and frame-synchronize are both picked up, and then de-multiplex. The FPGA in the receiver is divided into three modules which are digital PLL, data de-multiplexer and voltage display. The transmitter will multiplex four ways of 8-bit parallel data. The first way is ADC data, the second and the third way is generated by dip-key. The other is Barker code used for frame synchronizing. The receiver will maintain the bit synchronizing, recognize one frame and de-multiplex three ways data. The essay will discuss the design progress, the programming idea and some problems. Works have to be done by the designer are: Specify all system components, Make system specification, Draw system schematics, Write RTL code according the schematics, Synthesis and simulate the RTL code, Design the PCBs, Validate the functions of the FPGA on-line.
Keywords: DPLL; Frame-synchronize; TDM; Verilog HDL; Serial A/D convert;