基于VHDL数字频率计的设计与仿真

电子机电论文编号:JD133  字数:8993,页数:36

目 录
摘要 .....................................................................I
Abstract .................................................................Ⅱ
1 EDA、VHDL简介............................................................1
1.1 EDA技术................................................................1
1.2 硬件描述语言——VHDL ..................................................1
1.2.1 VHDL的简介.......................................................... 1
1.2.2 VHDL语言的特点 ......................................................2
1.2.3 VHDL的设计流程 ......................................................2
2.数字频率计的设计方案与功能实现 ..........................................4
2.1 数字频率计的基本原理...................................................4
2.2 数字频率计各模块的设计.................................................4
2.2.1 分频模块.............................................................5
2.2.2 主控模块 ............................................................6
2.2.3 寄存器模块.......................................................... 9
2.2.4 七段译码模块 .......................................................11
2.2.5 动态扫描模块 .......................................................12
2.2.6 数据选择器模块......................................................13
2.2.7 五进制计数分频模块 .................................................14
2.2.8 数字频率计总的原理图 ...............................................15
3 系统仿真 ...............................................................17
3.1 分频器模块仿真 .......................................................17
3.2 主控模块仿真..........................................................17
3.3 寄存器模块仿真 .......................................................19
3.4 七段译码显示模块仿真 .................................................19
3.5 数据选择器模块的仿真 .................................................20
3.6 动态扫描模块的仿真 ...................................................20
3.7 数字频率计总系统仿真 .................................................21
4 硬件仿真................................................................23
总结 .....................................................................24
致谢.....................................................................25
参考文献 .................................................................26
附录 .....................................................................27

摘 要
VHDL（Very High Speed Integrated Circuit Hardware Description Language,超高速集成电路硬件描述语言）诞生于1982年，是由美国国防部开发的一种快速设计电路的工具，目前已经成为IEEE（The Institute of Electrical and Electronics Engineers）的一种工业标准硬件描述语言。相比传统的电路系统的设计方法，VHDL具有多层次描述系统硬件功能的能力，支持自顶向下（Top to Down）和基于库（LibraryBased）的设计的特点。
本数字频率计是一种以VHDL（硬件描述性语言）为基础采用自顶而下设计方法实现的。该设计要能测量方波信号频率的频率计，测量结果用4位十进制数表示，频率测量范围分为四档，并用数码显示管显示其频率；同时设置了一个量程状态显示信号，在超出最大量程时报警。

关键字：VHDL语言,数字频率计, EDA技术，QUARTUSⅡ

Abstract
VHDL (Very High Speed Integrated Circuit Hardware Description Language, high-speed integrated circuit HDL) was born in 1982, is from the U.S. Department of Defense developed a fast circuit design tools, has now become the IEEE (The Institute of Electrical and Electronics Engineers) an industry-standard hardware description language. Compared to the traditional system of circuit design, VHDL description of a multi-level system hardware features the ability to support top-down (Top to Down) and based on the (LibraryBased) the design characteristics.
This is a digital frequency of the VHDL (hardware description language) based on a top-down design methods to realize. The design must be able to measure the frequency square-wave frequency of measurement results with four decimal number, frequency range is divided into Sidang and digital display shows the frequency at the same time set up a status display signal range in excess of the largest Alarm at the range.

Keywords: VHDL language,Digital frequency meter, EDA technology, QUARTUSⅡ